Non-volatile memory cells are well known in the art. A first type of prior art non-volatile memory cell 110 is shown in FIG. 1. The memory cell 110 comprises a semiconductor substrate 112 of a first conductivity type, such as P type. The substrate 112 has a surface on which there is formed a first region 114 (also known as the source line SL) of a second conductivity type, such as N type. A second region 116 (also known as the drain line) also of N type is formed on the surface of the substrate 112. Between the first region 114 and the second region 116 is a channel region 118. A bit line BL 120 is connected to the second region 116. A word line WL 122 is positioned above a first portion of the channel region 118 and is insulated therefrom. The word line 122 has little or no overlap with the second region 116. A floating gate FG 124 is over another portion of the channel region 118. The floating gate 124 is insulated therefrom, and is adjacent to the word line 122. The floating gate 124 is also adjacent to the first region 114. The floating gate 124 may overlap the first region 114 significantly to provide strong coupling from the region 114 into the floating gate 124.
One exemplary operation for erase and program of prior art non-volatile memory cell 110 is as follows. The cell 110 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the word line 122 and zero volts to the bit line and source line. Electrons tunnel from the floating gate 124 into the word line 122 causing the floating gate 124 to be positively charged, turning on the cell 110 in a read condition. The resulting cell erased state is known as ‘1’ state. The cell 110 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the source line 114, a small voltage on the word line 122, and a programming current on the bit line 120. A portion of electrons flowing across the gap between the word line 122 and the floating gate 124 acquire enough energy to inject into the floating gate 124 causing the floating gate 124 to be negatively charged, turning off the cell 110 in read condition. The resulting cell programmed state is known as ‘0’ state.
Exemplary voltages that can be used for the read, program, erase, and standby operations in memory cell 110 is shown below in Table 1:
TABLE 1OperationWLWL-unselBLBL-unselSLSL-unselReadVwlrd0 VVblrd0 V0 V0 VProgramVwlp0 VIprogVinhVslp0-1 V-FLTEraseVwler0 V0 V0 V0 V0 VStandby0 V0 V0 V0 V0 V0 VVwlrd ~2-3 VVblrd ~0.8-2 VVwlp ~1-2 VVwler ~11-13 VVslp ~9-10VFLT = floatIprog ~1-3 uaVinh ~2 V
A second type of prior art non-volatile memory cell 210 is shown in FIG. 2. The memory cell 210 comprises a semiconductor substrate 212 of a first conductivity type, such as P type. The substrate 212 has a surface on which there is formed a first region 214 (also known as the source line SL) of a second conductivity type, such as N type. A second region 216 (also known as the drain line) also of N type is formed on the surface of the substrate 212. Between the first region 214 and the second region 216 is a channel region 218. A bit line BL 220 is connected to the second region 216. A word line WL 222 is positioned above a first portion of the channel region 218 and is insulated therefrom. The word line 222 has little or no overlap with the second region 216. A floating gate FG 224 is over another portion of the channel region 218. The floating gate 224 is insulated therefrom, and is adjacent to the word line 222. The floating gate 224 is also adjacent to the first region 214. The floating gate 224 may overlap the first region 214 to provide coupling from the region 214 into the floating gate 224. A coupling gate CG (also known as control gate) 226 is over the floating gate 224 and is insulated therefrom.
One exemplary operation for erase and program of prior art non-volatile memory cell 210 is as follows. The cell 210 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the word line 222 with other terminals equal to zero volt. Electrons tunnel from the floating gate 224 into the word line 222 to be positively charged, turning on the cell 210 in a read condition. The resulting cell erased state is known as ‘1’ state. The cell 210 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate 226, a high voltage on the source line 214, and a programming current on the bit line 220. A portion of electrons flowing across the gap between the word line 222 and the floating gate 224 acquire enough energy to inject into the floating gate 224 causing the floating gate 224 to be negatively charged, turning off the cell 210 in read condition. The resulting cell programmed state is known as ‘0’ state.
Exemplary voltages that can be used for the read, program, erase, and standby operations in memory cell 210 is shown below in Table 2:
TABLE 2CG-unselectWL-BL-sameCG-SL-OperationWLunselectBLunselectCGsectorunselectSLunselectRead1.0-3 V0 V0.6-2 V0 V0-2.6 V0-2.6 V0-2.6 V0 V0 VErase11-10 V0 V0 V0 V0 V0 V0 V0 V0 VProgram1 V0 V1uAVinh8-11 V0-2.6 V0-2.6 V4.5-5 V0-1 V-FLT
Another set of exemplary voltages (when a negative voltage is available for read and program operations) that can be used for the read, program, and erase operations in memory cell 210 is shown below in Table 3:
TABLE 3CG-unselectWL-BL-sameCG-SL-OperationWLunselectBLunselectCGsectorunselectSLunselectRead1.0-2 V−0.5V/0 V0.6-2 V0 V0-2.6 V0-2.6 V0-2.6 V0 V0 VErase11-10 V0 V0 V0 V0 V0 V0 V0 V0 VProgram1 V−0.5 V/0 V1uAVinh8-11 V0-2.6 V0-2.6 V4.5-5 V0-1 V-FLT
Another set of exemplary voltages (when a negative voltage is available for read, program, and erase operations) that can be used for the read, program, and erase operations in memory cell 210 is shown below in Table 4:
TABLE 4CG-unselectWL-BL-sameCG-SL-Operation WLunselectBLunselectCGsectorunselectSLunselectRead1.0-2 V−0.5 V/0 V0.6-2 V0 V0-2.6 V0-2.6 V0-2.6 V0 V0 VErase9-6 V−0.5 V/0 V0 V0 V−(5-9) V0 V0 V0 V0 VProgram1 V−0.5 V/0 V1uAVinh8-9 V0-2.6 V0-2.6 V4.5-5 V0-1 V-FLT
A third type of non-volatile memory cell 310 is shown in FIG. 3. The memory cell 310 comprises a semiconductor substrate 312 of a first conductivity type, such as P type. The substrate 312 has a surface on which there is formed a first region 314 (also known as the source line SL) of a second conductivity type, such as N type. A second region 316 (also known as the drain line) also of N type is formed on the surface of the substrate 312. Between the first region 314 and the second region 316 is a channel region 318. A bit line BL 320 is connected to the second region 316. A word line WL 322 is positioned above a first portion of the channel region 318 and is insulated therefrom. The word line 322 has little or no overlap with the second region 316. A floating gate FG 324 is over another portion of the channel region 318. The floating gate 324 is insulated therefrom, and is adjacent to the word line 322. The floating gate 324 is also adjacent to the first region 314. The floating gate 324 may overlap the first region 314 to provide coupling from the region 314 into the floating gate 324. A coupling gate CG (also known as control gate) 326 is over the floating gate 324 and is insulated therefrom. An erase gate EG 328 is over the first region 314 and is adjacent to the floating gate 324 and the coupling gate 326 and is insulated therefrom. The top corner of the floating gate 324 may point toward the inside corner of the T-shaped erase gate 328 to enhance erase efficiency. The erase gate 328 is also insulated from the first region 314. The cell 310 is more particularly described in U.S. Pat. No. 7,868,375 whose disclosure is incorporated herein by reference in its entirety.
One exemplary operation for erase and program of prior art non-volatile memory cell 310 is as follows. The cell 310 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate 328 with other terminals equal to zero volt. Electrons tunnel from the floating gate 324 into the erase gate 328 causing the floating gate 324 to be positively charged, turning on the cell 310 in a read condition. The resulting cell erased state is known as ‘1’ state. The cell 310 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate 326, a high voltage on the source line 314, a medium voltage on the erase gate 328, and a programming current on the bit line 320. A portion of electrons flowing across the gap between the word line 322 and the floating gate 324 acquire enough energy to inject into the floating gate 324 causing the floating gate 324 to be negatively charged, turning off the cell 310 in read condition. The resulting cell programmed state is known as ‘0’ state.
Exemplary voltages that can be used for the read, program, and erase operations in memory cell 310 is shown below in Table 5:
TABLE 5CG-unselWL-BL-sameCG-EG-SL-OperationWLunselBLunselCGsectorunselEGunselSLunselRead1.0-2 V0 V0.6-2 V0 V0-2.6 V0-2.6 V0-2.6 V0-2.6 V0-2.6 V0 V0 VErase0 V0 V0 V0 V0 V0 V0 V11.5-12 V0-2.6 V0 V0 VProgram1 V0 V1uAVinh10-11 V0-5 V0-2.6 V4.5-8 V0-2.6 V4.5-5 V0-1 V-FLT
For programming operation, the EG voltage can be applied much higher, e.g. 8V, than the SL voltage, e.g., 5V, to enhance the programming operation. In this case, the unselected CG program voltage is applied at a higher voltage (CG inhibit voltage), e.g. 6V, to reduce unwanted erase effect of the adjacent memory cells sharing the same EG gate of the selected memory cells.
Another set of exemplary voltages (when a negative voltage is available for read and program operations) that can be used for the read, program, and erase operations in memory cell 310 is shown below in Table 6:
TABLE 6CG-unselBL-sameCG-EG-SL-OperationWLWL-unselBLunselCGsectorunselEGunselSLunselRead1.0-2 V−0.5V/0 V0.6-2 V 0 V0-2.6 V0-2.6 V0-2.6 V0-2.6 V0-2.6 V0 V0 VErase0 V0 V0 V0 V0 V0 V0 V11.5-12 V0-2.6 V0 V0 VProgram1 V−0.5V/0 V1uAVinh10-11 V0-2.6 V0-2.6 V4.5-5 V0-2.6 V4.5-5 V0-1 V-FLT
Another set of exemplary voltages (when a negative voltage is available for read, program, and erase operations) that can be used for the read, program, and erase operations in memory cell 310 is shown below in Table 7:
TABLE 7CG-unselWL-BL-sameCG-EG-SL-OperationWLunselBLunselCGsectorunselEGunselSLunselRead1.0-2 V−0.5 V/0 V0.6-2 V0 V0-2.6 V0-2.6 V0-2.6 V0-2.6 V0-2.6 V0 V0 VErase0 V−0.5 V/0 V0 V0 V−(5-9) V0 V0 V9-8 V0-2.6 V0 V0 VProgram1V−0.5 V/0 V1uAVinh8-9 V0-5V0-2.6 V8-9V0-2.6 V4.5-5 V0-1 V-FLT
For programming operation, the EG voltage is applied much higher, e.g. 8-9V, than the SL voltage, e.g., 5V, to enhance the programming operation. In this case, the unselected CG program voltage is applied at a higher voltage (CG inhibit voltage), e.g. 5V, to reduce unwanted erase effects of the adjacent memory cells sharing the same EG gate of the selected memory cells.
Memory cells of the types shown in FIGS. 1-3 typically are arranged into rows and columns to form an array. Erase operations are performed on entire rows or pairs of rows at one time, since word lines control entire rows of memory cells and erase gates (of the type shown in FIG. 3), when present, are shared by pairs of rows of memory cells.
For each of the prior art memory cells of FIGS. 1-3, and as can be seen in the above Tables, it often is necessary to pull the source line down to ground. FIG. 4 depicts a typical prior art technique for doing this. Memory system 400 comprises memory cell 410, word line 422, control gate 426, erase gate 428, bit line 420, and source line 414. Memory cell 410 can be any of the types shown in FIGS. 1-3, namely, memory cell 110, memory cell 210, memory cell 310, or another type of memory cell. Source line 414 is coupled to pull down transistor 430, which here comprises a single NMOS transistor. When the gate of pull down transistor 430 is activated, the source line is pulled down to ground. In a flash memory system, numerous pull down circuits of will be required, and each source line may require more than one pull down circuit. These pull down transistors require operating voltages of around 0-1.2 V for low voltage operations and 4-5-11.5 V for high voltage operations. This means that high voltage transistor type (e.g., 11.5v transistor) or IO transistor type (e.g., 2.5V or 3 v transistor) is required for the pull down transistors, which takes up die space and increases the overall cost and complexity of the system. In addition, the pull down transistors can incur over stress and break down during program mode.
What is needed is a new technique for pulling source lines to ground in a flash memory system that can use the same operating voltage range as the memory cells themselves and that are more robust to over stress and break down.